1. Field of the Invention
This invention relates generally to an apparatus and method for measuring electrical properties of a semiconductor wafer.
2. Description of Related Art
The determination of electrical properties of a dielectric on a semiconductor wafer and/or a carrier density profile within the semiconductor wafer is a critical factor in the production of these wafers. In order to determine the electrical properties of the wafer, various techniques may be employed, including a capacitance-voltage (CV) measurement technique, a current-voltage (IV) measurement technique, a conductance-voltage (GV) technique and/or capacitance-time (Ct) or lifetime measurement technique.
In some instances, the dopant concentration in the near surface region of a semiconductor surface must be profiled. Typically, in the absence of a metal oxide semiconductor (MOS) layer, this is accomplished using CV measurements, as applied to a Schottky barrier. A Schottky barrier is formed by applying a metal directly to the silicon or semiconductor material surface. However, the Schottky barrier formation process is tedious and time consuming. Further, CV measurements utilizing a Schottky barrier have five Debye length limitation (i.e., the dopant concentration can be profiled to within five Debye length from the surface). Alternatively, an oxide can be grown on the semiconductor material surface, and either a temporary or permanent metal contact can be made to the oxide surface to form a MOS junction. Utilizing a MOS junction yields superior performance, in that the doping concentration can be measured to within one Debye length from the oxide/material interface. However, in some cases, the user does not grow an oxide and, therefore, the Schottky method must be used.
Another problem with current measurement techniques stems from the electrical communication or interference between the object area or test site of the wafer and/or the probe with the surrounding region. The reduction of minority carrier generation from the surrounding region is required. Presently, this communication or interference is minimized by depositing a permanent guard ring 2 onto the oxide or dielectric surface surrounding a deposited test dot or object area 1. (See FIG. 1). However, the use of these deposited guard rings drastically increases processing times.
In order to map the semiconductor material surface, lateral movement between the probe and the wafer during CV and lifetime measurements is required. This lateral movement reduces mapping speeds. Still further, as discussed above, the measurements are subject to error due to interference from minority carriers.
It is, therefore, an object of the present invention to avoid or overcome the above problems and others by providing an apparatus for measuring the electrical properties of a semiconductor wafer having an improved probe configuration which minimizes interference or electrical communication from areas outside of the object area to the object area or the probe. It is another object of the present invention to provide a measurement apparatus that reduces mapping and measurement processing times and costs. Still further objects of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following description.